(1) Technical Field
This invention generally relates to electronic circuits, and more specifically to radio frequency (RF) switch circuits utilizing field effect transistors (FETs).
(2) Background
A recent trend in cellular radio architectures has been to incorporate a multiple pole FET-based RF switch architecture to accommodate multiple antennae, such that transmit and receive paths can connect to any selected antenna. This added flexibility has led to more complicated configurations of series and shunt RF FETs, requiring the need for novel topological innovations to overcome performance degradations in multiple pole FET switches. For example, in an RF switch architecture, when RF FETs are turned off and have high impedance paths to RF ground, certain impedance mismatch conditions can degrade signal insertion loss performance.
As an example, FIG. 1 is an equivalent-element schematic diagram of a typical prior art FET-based RF switch circuit 100 having two branches. Elements M1-M8 are implemented as FET switches. With respect to applied RF signals, each FET switch when “off” or “open” behaves as a capacitor, and when “on” or “closed” behaves as a conductive resistor. In the configuration shown, FET switches M1-M4 comprise a first branch 102 (for a port 104), and FET switches M5-M8 comprise a second branch 106 (for port 108). Either of the ports 104 or 108 may be coupled to antennas 110, 112 to conduct transmitted or received RF signals to connected circuitry (not shown).
In the configuration shown in FIG. 1, branch 102 is active, and port 104 is coupled to antenna 110 through FET switches M2 and M3, and isolated by FET switch M1 from antenna 112. However, if M1 is “closed” and M2 is “open”, then port 104 is coupled to antenna 112 through M1 and M3, and isolated by FET switch M2 from antenna 110. In both cases, branch 106 is inactive and FET switches M5 and M6 are open, nominally isolating port 108 from both antennas 110, 112. To couple port 108 to antenna 110, FET switches M1-M4 are set to the states shown in FIG. 1 for FET switches M5-M8, and FET switches M5-M8 are set to the states shown for FET switches M1-M4. Note also that when a port is coupled to an antenna, the other antenna may be connected to a different port or be left “floating” (as in the example shown in FIG. 1). Not shown are the control lines that synchronize state changes of the FET switches M1-M8, as described above. Of note is the fact that FET switches M7 and M8 are synchronously controlled to be in complementary states, so that FET switch M7 is always “open” when FET switch M8 is “closed”, and vice versa.
A problem arises because the switch circuit 100 of FIG. 1 has a capacitive connection between the antennas 110, 112. In particular, for the configuration shown in FIG. 1, there is a high impedance path from node X to ground through FET switches M7 and M8, since FET switches M5, M6, and M7 form a capacitor divider. In the illustrated state, this causes FET switches M5 and M6 to have a high impedance to RF ground when in the “open” (capacitive) state and increases the performance sensitivity to load mismatch on antenna 112.
FIG. 2 shows the insertion loss 200 of a signal path to one antenna (in dB) versus frequency for a 3:1 VSWR load on the unused antenna, swept across multiple phases, for a test implementation of the prior art switch circuit 100 shown in FIG. 1. For the particular test implementation of the switch circuit 100, the envelope of the insertion loss 200 showed a variability of up to 0.5 dB in the frequency range of interest (i.e., 0 GHz to 3 GHz in the illustrated example).
Accordingly, there is a need for a circuit and method for improving RF performance of FET-based circuits used in RF switch architectures. The present invention addresses this need.